The majority of present day integrated circuits (ICs) are implemented by using a plurality of interconnected field effect transistors (FETs), also called metal oxide semiconductor field effect transistors (MOSFETs or MOS transistors). A MOS transistor includes a gate electrode as a control electrode overlying a well in a semiconductor substrate and spaced-apart source and drain regions in the well between which a current can flow. In addition to MOS transistors, ICs often contain various additional devices such as, e.g., non-volatile memory (NVM) devices.
During formation of certain features in integrated circuits, such as NVM devices, electrical charges can build up and become trapped in isolated wells of the semiconductor substrate. For example, conventional NVM arrays are formed in and on isolated p-wells that are doped with p-type ions. The isolated p-wells are generally isolated by n-wells that are immediately adjacent to and beneath the isolated p-wells. As a result, electrical charges can become trapped in the isolated p-wells. During subsequent back-end-of-line (BEOL) fabrication of metallization layers, various metal features may be formed that are in electrical connection with the isolated p-wells and the adjacent n-wells, respectively. While the metal features that are in electrical connection with the isolated p-wells and the adjacent n-wells are ordinarily insulated from electrical communication with each other, surfaces of the metal features may be exposed during etching/cleaning and an electrical circuit may thus be completed between the isolated p-well and the adjacent n-wells by solvent (e.g., dilute hydrofluoric acid) employed to clean the various layers. As a result of forming the electrical circuit through the solvent, galvanic corrosion may occur in various metal features, especially in vias connecting to higher levels of metal layers where a significantly smaller number of vias are employed as compared to vias connecting to lower levels of metal layers. The galvanic corrosion leads to metal void formation in the affected metal features, ultimately resulting in compromised function of the integrated circuits. Additionally, galvanic corrosion is generally more prevalent in metal features that are in electrical communication with the isolated p-well.
The conventional approach to releasing the trapped electrical charges from isolated wells is to provide a tie-down diode in electrical communication with the isolated well and a ground. However, such diodes are not suitable for certain devices that employ high voltages during intended usage. The tie-down diodes function by discharging current when the voltage in the isolated well exceeds a design voltage of the tie-down diode. In NVM devices, relatively high voltages that generally exceed the voltage limits for the tie-down diodes are often employed during programming. Because tie-down diodes effectively release current upon exceeding the voltage threshold of the diodes, the maximum voltage that can be introduced into the isolated well is the voltage threshold of the tie-down diode and programming of the NVM devices would therefore not be possible with use of tie-down diodes.
Accordingly, it is desirable to provide integrated circuits that exhibit minimal metal void formation due to galvanic corrosion during fabrication of the integrated circuits without the use of tie-down diodes. Furthermore, other desirable features and characteristics will become apparent from the subsequent detailed description and the appended claims, taken in conjunction with the accompanying drawings and this background.